19 June, 2008 15:11
The contract is for a complete chip design comprising a bespoke 32,768-point FFT and associated functions and controls, including implementation of specialist algorithms, some proprietary Altera IP, conversion to floating-point magnitude format, and the serialisation of the buffered output data.
Reuse of some of RFEL's existing IP will also enable the design to be highly optimised, as well as meeting a demanding development timescale.
The extensive experience that RFEL has in this area of signal processing, coupled with the use of existing IP cores for FPGA, means that RFEL offered Thales a very cost effective and low risk route to achieving a critical processing element in the system.
The Thales overall system design approach will allow for the future upgrading of the system to accommodate developments in analogue to digital converter and other device enhancements, and so the RFEL design has also been structured in such a way as to accommodate these overall system changes.
Thales said, "The key part of the design was being able to pack as many functions into as small an FPGA as possible. RFEL's design is extremely compact and efficient and provides a relatively low-risk solution to alternative design approaches that we have considered."
"We're obviously very pleased to be working on another important project with the Thales team at Crawley and continuing a relationship that has existed for a number of years," said John Summers, RF Engines' CEO. "It does help to have good working relationships across all levels of the businesses, and, as always, a very clear set of requirements from the Thales team."
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RF Engines sign further contract with Thales UK
RF Engines (RFEL), the specialists in digital signal processing for FPGA, have been awarded a further contract by Thales' Land & Joint Systems Division for the rapid supply of a complex FFT-based design on a single Altera Cyclone II FPGA. The design is a key requirement for a new digital receiver design.The contract is for a complete chip design comprising a bespoke 32,768-point FFT and associated functions and controls, including implementation of specialist algorithms, some proprietary Altera IP, conversion to floating-point magnitude format, and the serialisation of the buffered output data.
Reuse of some of RFEL's existing IP will also enable the design to be highly optimised, as well as meeting a demanding development timescale.
The extensive experience that RFEL has in this area of signal processing, coupled with the use of existing IP cores for FPGA, means that RFEL offered Thales a very cost effective and low risk route to achieving a critical processing element in the system.
The Thales overall system design approach will allow for the future upgrading of the system to accommodate developments in analogue to digital converter and other device enhancements, and so the RFEL design has also been structured in such a way as to accommodate these overall system changes.
Thales said, "The key part of the design was being able to pack as many functions into as small an FPGA as possible. RFEL's design is extremely compact and efficient and provides a relatively low-risk solution to alternative design approaches that we have considered."
"We're obviously very pleased to be working on another important project with the Thales team at Crawley and continuing a relationship that has existed for a number of years," said John Summers, RF Engines' CEO. "It does help to have good working relationships across all levels of the businesses, and, as always, a very clear set of requirements from the Thales team."
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